1. Field of the Invention
The present invention relates to a device for reproducing a synchronizing clock signal from a series signal which has been modulated by coded modulation in synchronism with a clock signal of a prescribed period, the reproduced synchronizing clock signal being synchronous with the clock signal.
2. Description of the Prior Art
For transmitting digital data over a telephone line or a data line or recording digital data on a recording medium such as a magnetic disc, an optical disc, or the like, a practice widely used has been to modulate the digital data into a series signal encoded in synchronism with a clock signal of a prescribed period.
Examples of such encoding processes include NRZ (Nonreturn-to-Zero), NRZI (Nonreturn-to-Zero Inverted), PE (Phase Encoding), FM (Frequency Modulation), and MFM (Modified Frequency Modulation).
The signal encoded by these encoding methods is a code modulated by clock pulses (hereinafter referred to as a "bit clock") having a period equal to a data bit interval TB which is a time interval represenatative of one-bit data on a time-series basis. The interval of polarity inversion, the interval between positive-going edges, and the interval between negative-going edges of the encoded signal are each equal to a multiple of TB or TB/2.
For demodulating the encoded series signal to obtain the original data, it is often necessary to reproduce the bit clock used in the encoding process from the modulated signal. It is customary to reproduce clock pulses having the same period as that of the bit clock or a period equal to the period of the bit clock as divided by an integer, using a positive-going edge or a negative-going edge of a signal pulse, and to shift the phase of the reproduced clock pulses or frequency-divide the reproduced clock pulses to produce a demodulating synchronizing clock.
The synchronizing clock may typically be reproduced by one of the following two methods:
(1) A counter supplied as a clock input with a frequency that is a multiple (normally by 16 or 64) of that of the synchronizing clock is operated, and cleared by a positive-going edge or a negative-going edge of a signal pulse. The frequency-divided output of the counter is thus synchronized with the pulse signal edge, thereby reproducing the synchronizing clock.
(2) A bit clock insertion zone called a synchronizing field is provided in the initial portion of the modulated signal. A phase-locked loop circuit (hereinafter referred to as a "PLL circuit") is operated within the bit clock insertion zone to reproduce the synchronizing clock.
The circuit for carrying out the method (1) is very simple, but has problems in that jitter corresponding to one period of the clock input applied to the counter cannot be avoided, and the circuit tends to respond when the positive-going edge or negative-going edge of the modulated signal pulse is disturbed by noise.
The method (2) employs a feedback loop and has much better characteristics than those of the method (1) with respect to jitter and noise. However, this method requires a complex circuit since the synchronizing field is provided. Because synchronization is achieved basically only in the synchronizing field, a long-term nonsynchronous condition is apt to occur when a long continuous signal of more than several thousand bits is demodulated. This nonsynchronous condition has to be corrected by a suitable method.